A Novel High Performance Scan Architecture with Dmuxed Scan Flip-Flop (DSF) for Low Shift Power Scan Testing
نویسندگان
چکیده
منابع مشابه
Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop
Power consumption of any circuit is high during test mode than its normal mode of functioning. Different techniques are proposed to reduce the test power. This paper presents the consolidated research work carried to reduce the test power. Usually the power dissipation is due to the sequential and combinational elements presents in the circuit. In this paper we proposed different methodologies ...
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states at circuit nodes may erroneously change. Further, BIST schemes with random test patterns may need an excessive amount of energy because of longer test length. Abstract I n a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-path architecture called double-tree scan ...
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Serial scan design causes unnecessary switching activity during testing causing enormous power dissipation. The test time increases enormously with the increase in number of flip-flops. An alternate to serial scan architecture is Random Access Scan (RAS). Here every flip-flop is uniquely addressed using an address decoder. Although it may seem to have solved most of the current problems associa...
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In this paper, we present a low power architecture for scan-path. This architecture is suitable when it is used with a test compression. Based on data compression methodology, the vector set is partitioned so that the segments repeated in every scan can be removed. Here, it is not needed to change all bits of scan path during the new scan path where new test vector will be filled. In this way, ...
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High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This pap...
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ژورنال
عنوان ژورنال: Journal of Electrical Engineering and Technology
سال: 2009
ISSN: 1975-0102
DOI: 10.5370/jeet.2009.4.4.559